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Darsen D. Lu
Associate Professor in Institute of Microelectronics at National Cheng Kung University
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Researcher
Darsen D.
Lu
Associate Professor at National Cheng Kung University
Institute of Microelectronics
Tainan, Taiwan
Citations
-
Labs
Principal Investigator at
Semiconductor Device Modeling Laboratory 半導體元件模型實驗室
Labs
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https://www.impactio.com/researcher/DarsenDLu
Phone
+886 6 2757575 ext 62427
Email
darsenlu@mail.ncku.edu.tw
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Labs
Semiconductor Device Modeling Laboratory 半導體元件模型實驗室
Principal Investigator
Research Interests
Science
Compact Device Modeling for NCFET
Compact Device Modeling for the FinFET and UTBSOI MOSFETs
Hardware Realization of AI Deep Learning
Nanofabrication of M-I-M Devices for Resistive Memory Applications
Numerical Simulation of Semiconductor Processes and Devices FinFET (TCAD)
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Medicine
Engineering
Science
Bio-Resources & Agriculture
Public Health
Electrical Engineering & Computer Science
Life Science
Management
Law
Education
Social Sciences
Liberal Arts
+
Work Experience
Assistant Professor
National Cheng Kung University
August 2015 - Present
Taiwan
Department of Electrical Engineering
Research Scientist
IBM Thomas J. Watson Research Lab
August 2011 - August 2015
New York, USA
Research Intern
IBM Thomas J. Watson Research Lab
January 2010 - May 2010
New York, USA
Engineering Intern
IBM Semiconductor Research and Development Center
July 2008 - September 2009
New York, USA
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Currently working in this position
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Description
Education
University of California, Berkeley
USA
2011
PhD
Patents
Flash memory with multiple control gates and flash memory array device made thereof
Issued | Apr 14 2020 | US patent | #10622451
Other Inventors:
Darsen D. Lu
,
Y.-C. Wang
,
H.-K. Zeng
具有多個控制閘極的快閃記憶體與快閃記憶體陣列裝置
Pending | Jul 01 2019 | 中華民國發明專利 | I664715
Other Inventors:
Darsen D. Lu
,
Y.-C. Wang
,
H.-K. Zeng
Semiconductor structures having increased channel strain using fin release in gate regions
Pending | Apr 24 2018 | US patent | #9,954,083, #10,056,474, #10,347,752
Other Inventors:
K. Cheng
,
D. D. Lu
,
A. Reznicek
,
B. B. Doris
,
A. Khakifirooz
,
K. Rim
FinFET PCM access transistor having gate-wrapped source and drain regions
Pending | Nov 21 2017 | US patent | #9,825,094, 9,825,094
Other Inventors:
C. H. Lam
,
P. J. Oldiges
,
C.-H. Lin
,
D. D. Lu
FinFET with reduced parasitic capacitance
Pending | Oct 10 2017 | US patent | #9,786,737, #10,177,223
Other Inventors:
K. Cheng
,
T. Yamashita
,
D. D. Lu
,
X. Miao
Dielectrically isolated fin with improved fin profile
Pending | Jan 17 2017 | US patent | #9,548,213, #9,917,188
Other Inventors:
C. H. Lam
,
C.-H. Lin
,
D. D. Lu
,
A. Khakifirooz
,
K. Rim
Structure and method for compressively strained silicon germanium fins for pFET devices and tensily strained silicon fins for nFET devices
Pending | Jan 17 2017 | US patent | #9,548,386, #9,997,540
Other Inventors:
K. Cheng
,
B. B. Doris
,
A. Khakifirooz
,
D. D. Lu
,
A. Reznicek
,
K. Rim
Asymmetric FinFET memory access transistor
Pending | Jan 14 2017 | US patent | #9,583,624
Other Inventors:
C. H. Lam
,
C.-H. Lin
,
D. D. Lu
,
P. J. Oldiges
Strain release in pFET regions
Pending | Jan 10 2017 | US patent | #9,543,323, #9,761,610, #9,966,387
Other Inventors:
K. Cheng
,
B. B. Doris
,
A. Khakifirooz
,
D. D. Lu
,
A. Reznicek
,
K. Rim
Distributed decoupling capacitor
Pending | Sep 27 2016 | US patent | #9,455,250, #10,262,991
Other Inventors:
K. Cheng
,
A. Khakifirooz
,
D. D. Lu
,
G. Shahidi
Semiconductor device including dielectrically isolated finFETs and buried stressor
Pending | Jun 07 2016 | US patent | #9,362,400
Other Inventors:
K. Cheng
,
B. B. Doris
,
A. Khakifirooz
,
D. D. Lu
,
A. Reznicek
,
K. Rim
Structure and method for advanced bulk fin isolation
Pending | Mar 29 2016 | US patent | #9,299,618, #9,564,439, #9,583,492
Other Inventors:
K. Cheng
,
B. B. Doris
,
A. Khakifirooz
,
D. D. Lu
,
A. Reznicek
,
K. Rim
Structure and method to make strained FinFET with improved junction capacitance and low leakage
Pending | Mar 01 2016 | US patent | #9,276,113, #9,653,541
Other Inventors:
K. Cheng
,
B. B. Doris
,
A. Khakifirooz
,
D. D. Lu
,
A. Reznicek
,
K. Rim
Radiation tolerant device structure
Pending | Dec 06 2016 | US patent | #9,515,171
Other Inventors:
B. B. Doris
,
A. Khakifirooz
,
D. D. Lu
,
P. Oldiges
Lateral bipolar junction transistor having graded SiGe base
Pending | Dec 20 2016 | US patent | #9,525,027
Other Inventors:
P. Hashemi
,
A. Khakifirooz
,
D. Lu
,
A. Reznicek
,
D. Schepis
Method and structure for dielectric isolation in a fin field effect transistor
Pending | May 19 2015 | US patent | #9,034,715
Engineered substrate and device for co-integration of strained silicon and relaxed silicon
Pending | Dec 08 2015 | US patent | #9,209,065
Other Inventors:
K. Cheng
,
B. B. Doris
,
A. Khakifirooz
,
D. D. Lu
,
A. Reznicek
Project
AI於生醫之認知雲端與神經型態運算-應用於生醫影像之類神經電路驗證平台(2/4)
January 2019
-
December 2019
AI於生醫之認知雲端與神經型態運算-應用於生醫影像之類神經電路驗證平台(1/4)
January 2018
-
December 2018
電阻式記憶體元件特性及可靠度之統計模型
August 2016
-
July 2017
三維記憶體之金氧金整流元件奈米製程
February 2016
-
October 2016
Consulting Experience
National Cheng Kung University
Supervisor
|
2016
金屬-絕緣層-金屬 二極體之特性研究
逸軒, 陳. (Author).
2016 Aug 12
Student thesis
:
Master's Thesis
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